NXP Semiconductors /MIMXRT1062 /LCDIF /CTRL1_CLR

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Interpret as CTRL1_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NO_REQUEST)VSYNC_EDGE_IRQ 0 (NO_REQUEST)CUR_FRAME_DONE_IRQ 0 (NO_REQUEST)UNDERFLOW_IRQ 0 (NO_REQUEST)OVERFLOW_IRQ 0 (VSYNC_EDGE_IRQ_EN)VSYNC_EDGE_IRQ_EN 0 (CUR_FRAME_DONE_IRQ_EN)CUR_FRAME_DONE_IRQ_EN 0 (UNDERFLOW_IRQ_EN)UNDERFLOW_IRQ_EN 0 (OVERFLOW_IRQ_EN)OVERFLOW_IRQ_EN 0BYTE_PACKING_FORMAT 0 (IRQ_ON_ALTERNATE_FIELDS)IRQ_ON_ALTERNATE_FIELDS 0 (FIFO_CLEAR)FIFO_CLEAR 0 (START_INTERLACE_FROM_SECOND_FIELD)START_INTERLACE_FROM_SECOND_FIELD 0 (INTERLACE_FIELDS)INTERLACE_FIELDS 0 (RECOVER_ON_UNDERFLOW)RECOVER_ON_UNDERFLOW 0 (NO_REQUEST)BM_ERROR_IRQ 0 (BM_ERROR_IRQ_EN)BM_ERROR_IRQ_EN 0 (CS_OUT_SELECT)CS_OUT_SELECT 0 (IMAGE_DATA_SELECT)IMAGE_DATA_SELECT

CUR_FRAME_DONE_IRQ=NO_REQUEST, VSYNC_EDGE_IRQ=NO_REQUEST, BM_ERROR_IRQ=NO_REQUEST, OVERFLOW_IRQ=NO_REQUEST, UNDERFLOW_IRQ=NO_REQUEST

Description

LCDIF General Control1 Register

Fields

VSYNC_EDGE_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

0 (NO_REQUEST): No Interrupt Request Pending.

1 (REQUEST): Interrupt Request Pending.

CUR_FRAME_DONE_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

0 (NO_REQUEST): No Interrupt Request Pending.

1 (REQUEST): Interrupt Request Pending.

UNDERFLOW_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

0 (NO_REQUEST): No Interrupt Request Pending.

1 (REQUEST): Interrupt Request Pending.

OVERFLOW_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

0 (NO_REQUEST): No Interrupt Request Pending.

1 (REQUEST): Interrupt Request Pending.

VSYNC_EDGE_IRQ_EN

This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode

CUR_FRAME_DONE_IRQ_EN

This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

UNDERFLOW_IRQ_EN

This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

OVERFLOW_IRQ_EN

This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

BYTE_PACKING_FORMAT

This bitfield is used to show which data bytes in a 32-bit word are valid

IRQ_ON_ALTERNATE_FIELDS

If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

FIFO_CLEAR

Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

START_INTERLACE_FROM_SECOND_FIELD

The default is to grab the odd lines first and then the even lines

INTERLACE_FIELDS

Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

RECOVER_ON_UNDERFLOW

Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

BM_ERROR_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

0 (NO_REQUEST): No Interrupt Request Pending.

1 (REQUEST): Interrupt Request Pending.

BM_ERROR_IRQ_EN

This bit is set to enable bus master error interrupt in the LCDIF master mode.

CS_OUT_SELECT

This bit is CS0/CS1 valid select signals

IMAGE_DATA_SELECT

Command Mode MIPI image data select bit

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